A multiprocessor having a plurality of processor cores is widely used. Inside of the multiprocessor may be provided with a debug module which mainly debugs the processing operation of the processor cores. Generally, only one debug module is provided to the multiprocessor, and a plurality of processor cores are connected to this debug module. When one of the processor cores transits to the debug mode, device interrupts are generated to the other processor cores so that all of the processor cores transition to the debug mode. The debug module can be controlled from the outside of the multiprocessor through a JTAG interface standardized based on IEEE 1149.1.
When the number of processor cores is not so large, the multiprocessor having the conventional configuration can perform debug without any problem. However, as the number of processor cores increases the wire length between each processor core and the debug module becomes long since the multiprocessor has only one debug module, thereby increasing restrictions on timing due to the delay in signal transmission and making the wiring difficult.